High performance computer systems typically comprise a plurality of buses to transfer data between elements in the system. For example, a central processing unit (hereinafter "CPU") may conduct data transfers to a memory array through intermediate control logic. In one configuration, there may be two bus arrangements--one which couples the CPU to the control logic and one which couples the memory array to the control logic.
In such a system, the control logic performs the function of adapting the CPU bus protocol to the memory array bus protocol. Typically, the bandwidths, i.e., the amount of data that can be transferred per unit of time on a bus, of these two buses are unequal because of differences in protocol overhead, bus configuration and cycle times between the two buses. In order to maintain efficient and accurate data transfers between the CPU and the memory array, the control logic must equalize the bandwidths of these buses.
One solution for equalizing the bandwidth of the buses proposed by the prior art is to provide some form of buffering to store data received from either the CPU or the memory array at the proper operating speed. The data stored in the buffer is transmitted to its destination at the proper operating speed. However, if such buffering is provided, additional complex logic must be added to the control logic to prevent writes to the buffer when it is full thereby preventing buffer overrun. The stopping of data transfers to empty the buffer results in degradation of bus bandwidth and system performance.
Another solution is to introduce a number of dead, i.e., inactive, bus cycles on the bus operating at a higher bandwidth to equalize the bandwidths of the buses. Such a solution, however, results in a significant loss of bandwidth on both buses since the introduction of dead cycles will typically result in the system operating at a bandwidth lower than the bandwidth of the bus with the lower bandwidth.
While the prior art provides an adequate method for equalizing the bandwidths of two buses, there is a need for advancement. In particular, in a high performance computer system, a major bottleneck to processing speed is bus transfers. Thus, it is imperative to optimize the speed of bus transfers to improve the processing speed of the system.